Following in the footsteps of growing concern over US supply chain security and President Biden’s Executive Order to review critical US supply chains, DARPA has just announced its SAHARA program. The expanded acronym reads “Structured Array Hardware for Automatically Realized Applications”; the program aims to expand America’s domestic microchip production and development capability as well as improve overall chip security. To use the agency’s own words:
“Working in partnership with Intel and academic researchers from University of Florida, University of Maryland, and Texas A&M, SAHARA will leverage leading-edge, U.S.-based manufacturing capabilities to enable the automated and scalable conversion of defense-relevant field-programmable gate array (FPGAs) designs into quantifiably secure Structured ASICs. The program will also explore novel chip protections to support the manufacturing of silicon in zero-trust environments.”
FPGAs and ASICs are essentially two different technologies that, after decades of evolution, form the basis of most modern chip designs. The main difference is that FPGAs can be configured to fulfill multiple purposes at once while ASICs are designed to serve only one function. DARPA goes into more detail as to why it sees the future of military hardware in ASIC and why the technology is not more prevalent in current US military systems:
“While FPGAs are widely used in military applications today, Structured ASICs deliver significantly higher performance and lower power consumption, which makes them an efficient and effective alternative for defense electronic systems. Manually converting FPGAs to Structured ASICs, however, is a complex, lengthy, and costly process, making it difficult to justify the economic burden at the volume of custom chips required by DoD applications. Further, current conversion processes do not address design security considerations. To dramatically shorten the design process, reduce associated engineering costs, and enhance chip security, the Intel team will work to automate the conversion process for both currently fielded FPGAs as well as future capabilities, while adding unique chip protections to address supply chain security threats.”
The “protections” DARPA mentions take the form of “countermeasures capable of thwarting reverse engineering and counterfeiting attacks”. Verification, validation, and red teaming are all expected to be integrated into the next generation chips which will be reaching the defense industry with the support of the program.
On the engineering front, SAHARA is hoping to cut engineering costs of chips by 90%, reduce their power consumption by half, and to reduce design time by 60%.
The new DARPA microchip effort is critical to meeting the expectations laid out by the wider Department of Defense (DoD) microelectronics roadmap.